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DS80C310
PRELIMINARY
DS80C310 High-Speed Micro
FEATURES
PACKAGE OUTLINE
P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4/INT2 P1.5/INT3 P1.6/INT4 P1.7/INT5 RST P3.0/RXD0 P3.1/TXD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 40 39 38 37 36 35 34 33 VCC AD0 (P0.0) AD1 (P0.1) AD2 (P0.2) AD3 (P0.3) AD4 (P0.4) AD5 (P0.5) AD6 (P0.6) AD7 (P0.7) EA ALE PSEN A15 (P2.7) A14 (P2.6) A13 (P2.5) A12 (P2.4) A11 (P2.3) A10 (P2.2) A9 (P2.1) A8 (P2.0)
* 80C32 Compatible
- - - - - - 8051 pin and instruction set compatible Full duplex serial port Three 16-bit timer/counters 256 bytes scratchpad RAM Multiplexed address/data bus Addresses 64KB ROM and 64KB RAM
* High-Speed Architecture
- - - - - 4 clocks/machine cycle (8051 = 12) Runs DC to 33 MHz clock rates Single-cycle instruction in 121 ns Dual data pointer Optional variable length MOVX to access fast/ slow RAM /peripherals
* 10 total interrupt sources with 6 external * Internal power on reset circuit * Upwardly compatible with the DS80C320 * Available in 40-pin PDIP, 44-pin PLCC, and
44-pin TQFP
9 32 10 DALLAS 31 11 DS80C310 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 40-PIN DIP 6 1 40
7
39
DALLAS DS80C310
DESCRIPTION
The DS80C310 is a fast 80C31/80C32 compatible microcontroller. It features a redesigned processor core without wasted clock and memory cycles. As a result, it executes every 8051 instruction between 1.5 and 3 times faster than the original architecture for the same crystal speed. Typical applications will see a speed improvement of 2.5 times using the same code and the same crystal. The DS80C310 offers a maximum crystal speed of 33 MHz, resulting in apparent execution speeds of 82.5 MHz (approximately 2.5X).
17 18 33 44-PIN PLCC 28 23 29
34
22
DALLAS DS80C310
44 12
1 44-PIN TQFP
11
ECopyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books.
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DS80C310
The DS80C310 is pin compatible with the standard 80C32 and includes standard resources such as three timer/counters, 256 bytes of RAM, and a serial port. It also provides dual data pointers (DPTRs) to speed block data memory moves. It also can adjust the speed
of MOVX data memory access between two and nine machine cycles for flexibility in selecting external memory and peripherals. The DS80C310 offers upward compatibility with the DS80C320.
ORDERING INFORMATION:
PART NUMBER DS80C310-MCG DS80C310-QCG DS80C310-ECG DS80C310-MCL DS80C310-QCL DS80C310-ECL PACKAGE 40-pin plastic DIP 44-pin PLCC 44-pin TQFP 40-pin plastic DIP 44-pin PLCC 44-pin TQFP MAX. CLOCK SPEED 25 MHz 25 MHz 25 MHz 33 MHz 33 MHz 33 MHz TEMPERATURE RANGE 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
DS80C310 BLOCK DIAGRAM Figure 1
PORT LATCH
ACCUMULATOR
PORT 0
P1.0-P1.7
PORT 1
TIMER 2
ALU REG. 1
ALU REG. 2
DATA BUS
PSW ALU
STACK POINTER
DPTR1 INTERRUPT LOGIC TIMER 1
SERIAL PORT 0
PC ADDR. REG. TIMED ACCESS SFR RAM ADDRESS BUFFER 256 BYTES SFR 8 RAM
PC INCREMENT
ADDRESS BUS
P3.0-P3.7
PORT LATCH
INSTRUCTION DECODE
POWER CONTROL REG.
CLOCKS AND MEMORY CONTROL OSCILLATOR
RESET CONTROL
XTAL2
XTAL1
ALE
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PSEN
RST
P2.0-P2.7
PORT 3
PORT 2
INTERRUPT REG.
DPTR0
PORT LATCH
PROG. COUNTER
TIMER 0
AD0-AD7
B REGISTER
DS80C310
PIN DESCRIPTION Table 1
DIP 40 20 9 PLCC 44 22, 23, 1 10 TQFP 38 16, 17, 39 4 SIGNAL NAME VCC GND RST VCC - +5V. GND - Digital circuit ground. RST - Input. The RST input pin contains a Schmitt voltage input to recognize external active high reset inputs. The pin also employs an internal pull-down resistor to allow for a combination of wired OR external Reset sources. XTAL1, XTAL2 - The crystal oscillator pins XTAL1 and XTAL2 provide support for parallel resonant, AT cut crystals. XTAL1 acts also as an input in the event that an external clock source is used in place of a crystal. XTAL2 serves as the output of the crystal amplifier. PSEN - Output. The Program Store Enable output. This signal is commonly connected to external ROM memory as a chip enable. PSEN is active low. PSEN is driven high when data memory (RAM) is being accessed through the bus and during a reset condition. ALE - Output. The Address Latch Enable output functions as a clock to latch the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external 373 family transparent latch. ALE is forced high when the DS80C310 is in a Reset condition. AD0-7 (Port 0) - I/O. Port 0 is the multiplexed address/data bus. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls to a logic 0, the port transitions to a bidirectional data bus. This bus is used to read external ROM and read/write external RAM memory or peripherals. Port 0 has no true port latch and can not be written directly by software. The reset condition of Port 0 is high. Port 1 - I/O. Port 1 functions as both an 8-bit bidirectional I/O port and an alternate functional interface for Timer 2 I/O and new External Interrupts. The reset condition of Port 1 is with all bits at a logic 1. In this state, a weak pull-up holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pull-up. When software writes a 0 to any port pin, the DS80C310 will activate a strong pull-down that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pull-up. Once the momentary strong driver turns off, the port once again becomes the output high (and input) state. The alternate modes of Port 1 are outlined as follows: DESCRIPTION
18 19
20 21
14 15
XTAL2 XTAL1
29
32
26
PSEN
30
33
27
ALE
39 38 37 36 35 34 33 32 1-8
43 42 41 40 39 38 37 36 2-9
37 36 35 34 33 32 31 30 40-44 1-3
AD0 (P0.0) AD1 (P0.1) AD2 (P0.2) AD3 (P0.3) AD4 (P0.4) AD5 (P0.5) AD6 (P0.6) AD7 (P0.7) P1.0-P1.7
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DS80C310
DIP
PLCC
TQFP
SIGNAL NAME Port
DESCRIPTION Alternate Function T2 T2EX none none INT2 INT3 INT4 INT5 External I/O for Timer/Counter 2 Timer/Counter 2 Capture/Reload Trigger (DS80C320 has a serial port RXD) (DS80C320 has a serial port TXD) External Interrupt 2 (Positive Edge Detect) External Interrupt 3 (Negative Edge Detect) External Interrupt 4 (Positive Edge Detect) External Interrupt 5 (Negative Edge Detect)
1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28
2 3 4 5 6 7 8 9 24 25 26 27 28 29 30 31
40 41 42 43 44 1 2 3 18 19 20 21 22 23 24 25 A8 (P2.0) A9 (P2.1) A10 (P2.2) A11 (P2.3) A12 (P2.4) A13 (P2.5) A14 (P2.6) A15 (P2.7)
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
A8-15 (Port 2) - Output. Port 2 serves as the MSB for external addressing. P2.7 is A15 and P2.0 is A8. The DS80C310 will automatically place the MSB of an address on P2 for external ROM and RAM access. Although Port 2 can be accessed like an ordinary I/O port, the value stored on the Port 2 latch will never be seen on the pins (due to memory access). Therefore writing to Port 2, in software is only useful for the instructions MOVX A, @ Ri or MOVX @ Ri, A. These instructions use the Port 2 internal latch to supply the external address MSB. In this case, the Port 2 latch value will be supplied as the address information. Port 3 - I/O. Port 3 functions as both an 8-bit bi-directional I/O port and an alternate functional interface for external Interrupts, Serial Port 0, Timer 0 and 1 Inputs, RD and WR strobes. The reset condition of Port 3 is with all bits at a logic 1. In this state, a weak pull-up holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pull-up. When software writes a 0 to any port pin, the DS80C310 will activate a strong pull-down that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pull-up. Once the momentary strong driver turns off, the port once again becomes both the output high and input state. The alternate modes of Port 3 are outlined below. Port Alternate Mode RXD0 TXD0 INT0 INT1 T0 T1 WR RD Serial Port 0 Input Serial Port 0 Output External Interrupt 0 External Interrupt 1 Timer 0 External Input Timer 1 External Input External Data Memory Write Strobe External Data Memory Read Strobe
10-17
11, 13-19
5, 7-13
P3.0-P3.7
10 11 12 13 14 15 16 17 31 -
11 13 14 15 16 17 18 19 35 12 34
5 7 8 9 10 11 12 13 29 6 28 EA NC
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
EA - Input. This pin must be connected to ground for proper operation. NC - Reserved. These pins should not be connected. They are reserved for use with future devices in this family.
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DS80C310
COMPATIBILITY
The DS80C310 is a fully static CMOS 8051 compatible microcontroller designed for high performance. In most cases the DS80C310 can drop into an existing socket for the 80C31 or 80C32 to improve the operation significantly. In general, software written for existing 8051 based systems works without modification on the DS80C310. The exception is critical timing since the High-Speed Micro performs its instructions much faster than the original for any given crystal selection. The DS80C310 runs the standard 8051 family instruction set and is pin compatible with DIP, PLCC or TQFP packages. The DS80C310 is a streamlined version of the DS80C320. It maintains upward compatibility but has fewer peripherals. The DS80C310 provides three 16-bit timer/counters, a full-duplex serial port, and 256 bytes of direct RAM. I/O ports have the same operation as a standard 8051 product. Timers will default to a 12 clock per cycle operation to keep their timing compatible with original 8051 family systems. However, timers are individually programmable to run at the new 4 clocks per cycle if desired. The DS80C310 provides several new hardware functions that are controlled by Special Function registers. A summary of the Special Function Registers is provided in Table 2.
individual programs will depend on the actual instructions used. Speed sensitive applications would make the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any code. These architecture improvements and 0.8 m CMOS produce a peak instruction cycle in 121 ns (8.25 MIPs). The Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARY
All instructions in the DS80C310 perform the same functions as their 8051 counterparts. Their effect on bits, flags, and other status functions is identical. However, the timing of each instruction is different. This applies both in absolute and relative number of clocks. For absolute timing of real-time events, the timing of software loops can be calculated using a table in the High-Speed Microcontroller User's Guide. However, counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor operation. The relative time of two instructions might be different in the new architecture than it was previously. For example, in the original architecture, the "MOVX A, @DPTR" instruction and the "MOV direct, direct" instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS80C310, the MOVX instruction takes as little as two machine cycles or eight oscillator cycles but the "MOV direct, direct" uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the DS80C310 usually uses one instruction cycle for each instruction byte. The user concerned with precise program timing should examine the timing of each instruction for familiarity with the changes. Note that a machine cycle now requires just four clocks, and provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the original architecture, all were one or two cycles except for MUL and DIV. Refer to the High-Speed Microcontroller User's Guide for details and individual instruction timing.
PERFORMANCE OVERVIEW
The DS80C310 features a high-speed 8051 compatible core. Higher speed comes not just from increasing the clock frequency, but from a newer, more efficient design. This updated core does not have the dummy memory cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS80C310, the same machine cycle takes four clocks. Thus the fastest instruction, 1 machine cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions. The majority of instructions on the DS80C310 will see the full 3 to 1 speed improvement. Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the original 8051. The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
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DS80C310
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special features of the DS80C310. The High-Speed Microcontroller User's Guide describes all SFRs. Functions that are not part of the standard 80C32 are in bold.
SPECIAL FUNCTION REGISTERS Table 2
REGISTER SP DPL DPH DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 EXIF SCON SBUF P2 IE SADDR0 P3 IP SADEN0 STATUS T2CON T2MOD RCAP2L RCAP2H TL2 TH2 PSW WDCON ACC EIE B EIP - - - - PX5 PX4 PX3 PX2 - - - - EX5 EX4 EX3 EX2 CY - AC POR F0 - RS1 - RS0 - OV - FL - P - 0 TF2 - HIP EXF2 - LIP RCLK - 1 TCLK - 1 EXEN2 - 1 TR2 - 1 C/T2 T2OE 1 CP/RL2 DCEN P3.7 - P3.6 - P3.5 PT2 P3.4 PS0 P3.3 PT1 P3.2 PX1 P3.1 PT0 P3.0 PX0 P2.7 EA P2.6 - P2.5 ET2 P2.4 ES0 P2.3 ET1 P2.2 EX1 P2.1 ET0 P2.0 EX0 - P1.7 IE5 SM0/FE - P1.6 IE4 SM1 T2M P1.5 IE3 SM2 T1M P1.4 IE2 REN T0M P1.3 - TB8 MD2 P1.2 - RB8 MD1 P1.1 - TI MD0 P1.0 - RI 0 SMOD TF1 GATE 0 SMOD0 TR1 C/T 0 - TF0 M1 0 - TR0 M0 0 GF1 IE1 GATE 0 GF0 IT1 C/T 0 STOP IE0 M1 SEL IDLE IT0 M0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 90h 91h 98h 99h A0h A8h A9h B0h B8h B9h C5h C8h C9h CAh CBh CCh CDh D0h D8h E0h E8h F0h F8h
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DS80C310
MEMORY ACCESS
The DS80C310 contains no on-chip ROM, and 256 bytes of scratchpad RAM. Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. Timing diagrams are provided in the Electrical Specifications. Program memory (ROM) is accessed at a fixed rate determined by the crystal frequency and the actual instructions. As mentioned above, an instruction cycle requires four clocks. Data memory (RAM) is accessed according to a variable speed MOVX instruction as described below.
nine machine cycles. Software can dynamically change this value depending on the particular memory or peripheral. On reset, the Stretch value will default to a one resulting in a three cycle MOVX. Therefore, RAM access will not be performed at full speed. This is a convenience to existing designs that may not have fast RAM in place. When maximum speed is desired, the software should select a Stretch value of zero. When using very slow RAM or peripherals, a larger stretch value can be selected. Note that this affects data memory only and the only way to slow program memory (ROM) access is to use a slower crystal. Using a Stretch value between one and seven causes the microcontroller to stretch the read/write strobe and all related timing. This results in a wider read/write strobe allowing more time for memory/peripherals to respond. The timing of the variable speed MOVX is shown in the Electrical Specifications. Note that full speed access is not the reset default case. Table 3 shows the resulting strobe widths for each Stretch value. The memory stretch is implemented using the Clock Control Special Function Register at SFR location 8Eh. The stretch value is selected using bits CKCON.2-0. In the table, these bits are referred to as M2 through M0. The first stretch (default) allows the use of common 120 ns or 150 ns RAMs without dramatically lengthening the memory access.
STRETCH MEMORY CYCLE
The DS80C310 allows the application software to adjust the speed of data memory access. The micro is capable of performing the MOVX in as few as two instruction cycles. However, this value can be stretched as needed so that both fast memory and slow memory or peripherals can be accessed with no glue logic. Even in high- speed systems, it may not be necessary or desirable to perform data memory access at full speed. In addition, there are a variety of memory mapped peripherals such as LCD displays or UARTs that are not fast. The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below. This allows the user to select a stretch value between zero and seven. A Stretch of zero will result in a two machine cycle MOVX. A Stretch of seven will result in a MOVX of
DATA MEMORY CYCLE STRETCH VALUES Table 3
CKCON.2-0 M2 M1 M0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MEMORY CYCLES 2 3 (default) 4 5 6 7 8 9 RD OR WR STROBE WIDTH IN CLOCKS 2 4 8 12 16 20 24 28 STROBE WIDTH TIME @ 25 MHz @ 33 MHz 80 ns 160 ns 320 ns 480 ns 640 ns 800 ns 960 ns 1120 ns 60 ns 121 ns 242 ns 364 ns 485 ns 606 ns 727 ns 848 ns
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DS80C310
DUAL DATA POINTER
Data memory block moves can be accelerated using the DS80C310 Dual Data Pointer (DPTR). The standard 8032 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the DS80C310, the standard data pointer is called DPTR and is located at SFR addresses 82h and 83h. These are the standard locations. No modification of standard code is needed to use DPTR. The new DPTR is located at SFR 84h and 85h and is called DPTR1. The DPTR Select bit (DPS) chooses the active pointer and is located at the lsb of the SFR location 86h. No other bits in register 86h have any effect and are set to 0. The user switches between data pointers by toggling the lsb of register 86h. The increment (INC) instruction is the fastest way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any activity. Therefore only one instruction is required to switch from a source to a destination address. Using the Dual Data Pointer saves code from needing to save source and destination addresses when doing a block move. Once loaded, the software simply switches between DPTR0 and 1. The relevant register locations are as follows. DPL DPH DPL1 DPH1 DPS 82h 83h 84h 85h 86h Low byte original DPTR High byte original DPTR Low byte new DPTR High byte new DPTR DPTR Select (lsb)
TIMER RATE CONTROL
There is one important difference between the DS80C310 and 8051 regarding timers. The original 8051 used 12 clocks per cycle for timers as well as for machine cycles. The DS80C310 architecture normally uses 4 clocks per machine cycle. However, in the area of timers and serial ports, the DS80C310 will default to 12 clocks per cycle on reset. This allows existing code with real-time dependencies such as baud rates to operate properly. If an application needs higher speed timers or serial baud rates, the user can select individual timers to run at the 4 clock rate. The Clock Control register (CKCON; 8Eh) determines these timer speeds. When the relevant CKCON bit is a logic 1, the DS80C310 uses 4 clocks per cycle to generate timer speeds. When the bit is a 0, the DS80C310 uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0. Note that unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls are independent.
POWER ON RESET
The DS80C310 will hold itself in reset during a power up until 65,536 clock cycles have elapsed. The power-on reset used by the DS80C310 differs somewhat from other members of the High-Speed Microcontroller family. The crystal oscillator may start anywhere between 1.0V and 4.5V, but is not specified. This eliminates the need for an RC reset circuit. For voltage specific precision brownout detection, an external component will be needed. When the device goes through a power on reset, the POR flag will be set in the WDCON (D8h) register at bit 6.
STOP MODE ENHANCEMENTS
Setting bit 1 of the Power Control register (PCON; 87h) invokes the Stop mode. Stop mode is the lowest power state since it turns off all internal clocking. The ICC of a standard Stop mode is approximately 1 A (but is specified in the Electrical Specifications). The CPU will exit Stop mode from an external interrupt or a reset condition. Internally generated interrupts are not useful since they require clocking activity. The DS80C310 allows a resume from Stop using a INT2-5, which are edge triggered interrupts. The start-up timing is managed by an internal crystal counter. A delay of 65,536 clocks occurs to give the crystal enough time to start and stabilize.
INTERRUPTS
The DS80C310 provides 10 interrupt sources with two priority levels. Software can assign high or low priority to all sources. All interrupts that are new to the 8051 have a lower natural priority than the originals.
PERIPHERAL OVERVIEW
The DS80C310 provides the same peripheral functions as the standard 80C32. It is compatible with the DS80C320 but does not offer all of the peripherals.
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DS80C310
INTERRUPT SOURCES AND PRIORITIES Table 4
NAME INT0 TF0 INT1 TF1 SCON TF2 INT2 INT3 INT4 INT5 DESCRIPTION External Interrupt 0 Timer 0 External Interrupt 1 Timer 1 TI or RI from the serial port Timer 2 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 VECTOR 03h 0Bh 13h 1Bh 23h 2Bh 43h 4Bh 53h 5Bh NATURAL PRIORITY 1 2 3 4 5 6 7 8 9 10
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DS80C310
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Supply Current Active Mode @ 33 MHz Supply Current Idle Mode @ 33 MHz Supply Current Stop Mode Input Low Level Input High Level Input High Level XTAL1 and RST Output Low Voltage Ports 1, 3 @ IOL=1.6 mA Output Low Voltage Port 0, 2, ALE, PSEN @ IOL=3.2 mA Output High Voltage Ports 1, 3, ALE and PSEN @ IOH= -50 A Output High Voltage @ IOH=-1.5 mA Ports 1, 3 Output High Voltage Ports 0, 2, ALE, PSEN @ IOH= -8 mA Input Low Current Ports 1, 3 @ 0.45V Transition Current from 1 to 0 Ports 1, 3 @ 2V Input Leakage Port 0, Bus Mode RST Pull-Down Resistance SYMBOL VCC ICC IIDLE ISTOP VIL VIH VIH2 VOL1 VOL2 VOH1 VOH2 VOH3 IIL ITL IL RRST -300 50 2.4 2.4 2.4 -0.3 2.0 3.5 0.15 0.15 MIN 4.0 TYP 5.0 30 15 1
(0C to 70C; VCC=4.0V to 5.5V)
MAX 5.5 UNITS V mA mA A +0.8 VCC+0.3 VCC+0.3 0.45 0.45 V V V V V V V V -55 -650 300 170 A A A K 8 9 NOTES 1 2 3 4 1 1 1 1 1, 5 1, 6 1, 7 1, 5
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted. 1. All voltages are referenced to ground. 2. Active current is measured with a 33 MHz clock source driving XTAL1, VCC=RST=5.5V, all other pins disconnected. 3. Idle mode current is measured with a 33 MHz clock source driving XTAL1, VCC=5.5V, RST at ground, all other pins disconnected.
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DS80C310
4. Stop mode current measured with XTAL1 and RST grounded, VCC=5.5V, all other pins disconnected. 5. When addressing external memory. 6. RST=VCC. This condition mimics operation of pins in I/O mode. 7. During a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition mode. 8. Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approximately 2V. 9. 0.45TYPICAL ICC VERSUS FREQUENCY Figure 2
ICC mA 30 @ 5V
25
20
15
5 3 2 0 2 4 6 8 10 12 16 20 24 30 33 MHz XTAL FREQUENCY
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DS80C310
AC ELECTRICAL CHARACTERISTICS
25 MHz PARAMETER Oscillator Frequency ALE Pulse Width Port 0 Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instr. In Input Instruction Hold after PSEN Input Instruction Float after PSEN Port 0 Address to Valid Instr. In Port 2 Address to Valid Instr. In PSEN Low to Address Float SYMBOL 1/tCLCL tLHLL tAVLL tLLAX1 tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV1 tAVIV2 tPLAZ 0 26 71 81 0 10 55 41 MIN 0 40 10 10 56 MAX 33
(0C to 70C; VCC=4.0V to 5.5V)
VARIABLE CLOCK MIN 0 1.5tCLCL-5 0.5tCLCL-5 0.5tCLCL-5 2.5tCLCL-20 0.5tCLCL-5 2tCLCL-5 2tCLCL-20 0 tCLCL-5 3tCLCL-20 3.5tCLCL-25 0 MAX 33 NOTES MHz ns ns ns ns ns ns ns ns ns ns ns ns
NOTES FOR AC ELECTRICAL CHARACTERISTICS
All parameters apply to both commercial and industrial temperature range operation unless otherwise noted. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN, RD and WR with 100 pF. Interfacing to memory devices with float times (turn off times) over 25 ns may cause contention. This will not damage the parts, but will cause an increase in operating current.
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DS80C310
MOVX CHARACTERISTICS
PARAMETER Data Access ALE Pulse Width Address Hold after ALE Low for MOVX Write RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold after Read Data Float after Read ALE Low to Valid Data In Port 0 Address to Valid Data In Port 2 Address to Valid Data In ALE Low to RD or WR Low Port 0 Address to RD or WR Low Port 2 Address to RD or WR Low Data Valid to WR Transition Data Hold after Write RD Low to Address Float RD or WR High to ALE High SYMBOL tLLHL2 tLLAX2 tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV1 tAVDV2 tLLWL tAVWL1 tAVWL2 tQVWX tWHQX tRLAZ tWHLH 0 tCLCL-5 0.5tCLCL-5 tCLCL-5 tCLCL-5 2tCLCL-5 1.5tCLCL-10 2.5tCLCL-10 -5 tCLCL-5 2tCLCL-5 0 MIN 1.5tCLCL-5 2tCLCL-5 0.5tCLCL-5 tCLCL-5 2tCLCL-5 tMCS-10 2tCLCL-5 tMCS-10
(0C to 70C; VCC=4.0V to 5.5V)
VARIABLE CLOCK MAX UNITS ns ns ns ns 2tCLCL-20 tMCS-20 tCLCL-5 2tCLCL-5 2.5tCLCL-20 tCLCL+tMCS-40 3tCLCL-20 1.5tCLCL+tMCS-20 3.5tCLCL-20 2tCLCL+tMCS-20 0.5tCLCL+5 tCLCL+5 ns ns ns ns ns ns ns ns ns ns ns -0.5tCLCL-5 10 tCLCL+5 ns ns tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS=0 tMCS>0 STRETCH tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0
NOTE: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for each Stretch selection. M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 MOVX CYCLES 2 machine cycles 3 machine cycles (default) 4 machine cycles 5 machine cycles 6 machine cycles 7 machine cycles 8 machine cycles 9 machine cycles tMCS 0 4 tCLCL 8 tCLCL 12 tCLCL 16 tCLCL 20 tCLCL 24 tCLCL 28 tCLCL
031296 13/21
DS80C310
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER Clock High Time Clock Low Time Clock Rise Time Clock Fall Time SYMBOL tCHCX tCLCX tCLCL tCHCL MIN 10 10 TYP
(0C to 70C; VCC=4.0V to 5.5V)
MAX UNITS ns ns 5 5 ns ns NOTES
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER Serial Port Clock Cycle Time SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Output Data Setup to Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Output Data Hold from Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Input Data Hold after Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Clock Rising Edge to Input Data Valid SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle SYMBOL tXLXL 12tCLCL 4tCLCL tQVXH 10tCLCL 3tCLCL tXHQX 2tCLCL tCLCL tXHDX tCLCL tCLCL tXHDV 11tCLCL 3tCLCL MIN TYP
(0C to 70C; VCC=4.0V to 5.5V)
MAX UNITS ns ns ns ns ns ns ns ns NOTES
ns ns
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. For completeness, the following is an explanation of the symbols. t A C D H L I P Q R V W X Z Time Address Clock Input data Logic level high Logic level low Instruction PSEN Output data RD signal Valid WR signal No longer a valid logic level Tristate
031296 14/21
DS80C310
EXTERNAL PROGRAM MEMORY READ CYCLE
tLHLL tLLIV ALE tAVLL tPLPH tPLIV PSEN
tLLPL tPLAZ tLLAX1 tPXIX tPXIZ
PORT 0
ADDRESS A0-A7 tAVIV1 tAVIV2
INSTRUCTION IN
ADDRESS A0-A7
PORT 2
ADDRESS A8-A15 OUT
ADDRESS A8-A15 OUT
EXTERNAL DATA MEMORY READ CYCLE
tLLDV
ALE tWHLH tLLWL PSEN RD tAVLL tRLAZ tAVWL1 tRHDZ tRHDX tLLAX1 tRLRH tRLDV
PORT 0
INSTRUCTION IN
ADDRESS A0-A7 tAVDV1 tAVDV2
DATA IN
ADDRESS A0-A7
PORT 2
ADDRESS A8-A15 OUT
tAVWL2
031296 15/21
DS80C310
DATA MEMORY WRITE CYCLE
ALE tWHLH tLLWL PSEN tLLAX2 tWLWH WR tAVLL tWHQX
PORT 0
INSTRUCTION IN
ADDRESS A0-A7 tQVWX tAVWL1
DATA OUT
ADDRESS A0-A7
PORT 2
ADDRESS A8-A15 OUT
tAVWL2
DATA MEMORY WRITE WITH STRETCH=1
Last Cycle of Previous Instruction First Machine Cycle Second Machine Cycle MOVX Instruction C1 CLK C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 Third Machine Cycle Next Instruction Machine Cycle
ALE
PSEN
WR
PORT 0
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
MOVX Instruction Address
Next Instr. Address MOVX Instruction Next Instruction Read A8-A15
MOVX Data Address
MOVX Data
PORT 2
A8-A15
A8-A15
A8-A15
031296 16/21
DS80C310
DATA MEMORY WRITE WITH STRETCH=2
Last Cycle of Previous Instruction First Machine Cycle Second Machine Cycle Third Machine Cycle Fourth Machine Cycle Next Instruction Machine Cycle C4 C1 C2 C3 C4
MOVX Instruction C1 CLK C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3
ALE
PSEN WR
PORT 0
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
A0-A7
D0-D7
MOVX Instruction Address
Next Instr. Address MOVX Instruction Next Instruction Read A8-A15
MOVX Data Address
MOVX Data
PORT 2
A8-A15
A8-A15
A8-A15
FOUR CYCLE DATA MEMORY WRITE STRETCH VALUE=2
EXTERNAL CLOCK DRIVE
tCLCL
tCHCX XTAL1 tCHCL tCLCX tCLCH
031296 17/21
DS80C310
SERIAL PORT MODE 0 TIMING
SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL/4
ALE PSEN tQVXL WRITE TO SBUF RXD DATA OUT TXD CLOCK tXLXL TI WRITE TO SCON TO CLEAR RI RXD DATA IN TXD CLOCK RI tXHDV tXHDX
D0 D1 D2 D3 D4 D5 D7 D8 D0
tXHQX
D1 D2 D3 D4 D5 D7 D8
TRANSMIT
RECEIVE
SERIAL PORT 0 (SYNCHRONOUS MODE) SM2=0=>TXD CLOCK=XTAL/12
ALE PSEN 1/(XTAL FREQ/12) WRITE TO SBUF TRANSMIT RXD DATA OUT TXD CLOCK TI WRITE TO SCON TO CLEAR RI RECEIVE RXD DATA IN TXD CLOCK RI
D0 D1 D6 D7 D0 D1 D6 D7
031296 18/21
DS80C310
40-PIN PDIP (600 MIL)
ALL DIMENSIONS ARE IN INCHES.
PKG DIM A A1 A2 b c D E E1 e L eB
40-PIN MIN - 0.015 0.140 0.014 0.008 1.980 0.600 0.530 0.090 0.115 0.600 MAX 0.200 - 0.160 0.022 0.012 2.085 0.625 0.555 0.110 0.145 0.700
56-G5000-000
031296 19/21
DS80C310
44-PIN PLCC
PKG DIM A A1 A2 B B1 c CH1 D D1 D2 E E1 E2 e1 N
44-PIN MIN 0.165 0.090 0.020 0.026 0.013 0.009 0.042 0.685 0.650 0.590 0.685 0.650 0.590 MAX 0.180 0.120 - 0.033 0.021 0.012 0.048 0.695 0.656 0.630 0.695 0.656 0.630
0.050 BSC 44 -
56-G4003-001
031296 20/21
DS80C310
44-PIN TQFP
1
PKG DIM A A1 A2 D D1 E E1 L e B C
44-PIN MIN - 0.05 0.95 11.80 MAX 1.20 0.15 1.05 12.20
10.00 BSC 11.80 12.20
10.00 BSC 0.45 0.75
0.80 BSC 0.30 0.09 0.45 0.20
56-G4012-001
031296 21/21

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